Software Developer and Research Fellow at H2020 (EPI2, TextaRossa, EuPilot)
Ph.D. Candidate and Teaching Assistant at University of Pisa
<aside> <img src="/icons/mail_lightgray.svg" alt="/icons/mail_lightgray.svg" width="40px" /> federico.rossi[at]ing.unipi.it
</aside>
<aside> <img src="https://s3-us-west-2.amazonaws.com/secure.notion-static.com/82e28110-6dce-430c-a77e-90020c35fee5/GitHub-Mark.png" alt="https://s3-us-west-2.amazonaws.com/secure.notion-static.com/82e28110-6dce-430c-a77e-90020c35fee5/GitHub-Mark.png" width="40px" /> federicorossifr@github
</aside>
<aside> <img src="https://s3-us-west-2.amazonaws.com/secure.notion-static.com/e1c0661b-8a74-4ef9-9cfb-2679c7407b7b/new-linkedin-logo-white-black-png.png" alt="https://s3-us-west-2.amazonaws.com/secure.notion-static.com/e1c0661b-8a74-4ef9-9cfb-2679c7407b7b/new-linkedin-logo-white-black-png.png" width="40px" /> federicorossifr@linkedin
</aside>
Ph.D. Candidate and Researcher at University of Pisa. I am currently working on compression and compressed alternative floating-point formats for machine learning and HPC applications in ARM/RISCV environments. I am also involved as Software Developer and Research Fellow in the H2020 and EuroHPC European Projects EPI2, TextaRossa and EuPilot.
Machine Learning | Research Fellow EuPilot: Pilot using Independent Local & Open Technologies ~ Dec 2021 - Now
Researcher and developer in the WP4.2 "AI Video Processing" work package.
Hardware/Software Developer | Research Fellow TEXTAROSSA ~ Apr 2021 - Now
Responsible for the WP2.1 "Accelerators with mixed-precision" work package.
Design and development of an IP for mixed precision computing and compression exploiting Posit arithmetic
HPC Software Developer | Research Fellow EPI ~ September 2019 - Dec 2021 | EPI2 ~ January 2022 - Now
Development of compressed alternative floating-point formats for machine learning and HPC applications in the ARM/RISCV environments. Opimization and vectorization of Machine Learning algorithms. Multi-node and multi-core distributed machine learning kernels (OpenMPI/OpenMP)
- Software/Hardware Designer: Development of a RISC-V instruction set extension, relative emulation software, compiler support. Design, synthesys and FPGA implementation of a posit accelerator unit for the ARIANE RISC-V core.
- C++ Developer: Development and mainteinment of a modern C 14 library for high-performance alternative real number computation. Including multi-architecture and architecture specific accelerators for ARM Scalable Vector Extension and RISC-V "V" extension.
- C++ Developer: Development of a deep neural network based benchmark suite for the European Processor Initiative framework. The library includes architecture-specific implementation for ARM Scalable Vector Extension, RISC-V "V" extension and OpenMPI platform.
Design and development of a hardware accelerator for posit arithmetic. Application of mixed precision computation to seismic wavefront analysis.
Teaching assistant University of Pisa ~ Marzo 2021 - Now
Teaching assistant for the Symbolic and Evolutionary Artificial Intelligence course: Hardware Accelerators for Artificial Intelligence
Supervised students
Francesco Urbani, Master Degree in Electronic Engineering, “Design and Hardware Implementation of a Pipelined Posit Arithmetic Core Generator”
